WESDAC D20 PS GE VMEbus system controller

System Controller: The VMEbus system controller capabilities allow
the board to operate as a slot 1 controller, or it may be disabled when
another board is acting as the system controller. The system controller
may be programmed to provide the following modes of arbitration:
Round Robin (RRS)
Single Level (SGL)
Priority (PRI)
The system controller provides a SYSCLK driver, IACK* daisy-chain
driver, and a VMEbus access timeout timer. The system controller also
provides an arbitration timeout if BBSY* is not seen within a specified
period after a BGOUT* signal is issued. This period is programmable for
16 or 256 µs.
VMEbus Requester: The microprocessor can request and gain control
of the bus using any of the VMEbus request lines (BR3* to BR0*) under
software control. The requester can be programmed to operate in any of
the following modes:
Release-On-Request (ROR)
Release-When-Done (RWD)
VMEbus Capture and Hold (VCAP)
Mailboxes: The VMEbus interface provides four 32-bit mailboxes,
which are accessible from both the microprocessor and the VMEbus
providing interprocessor communication. The mailboxes have the ability
to interrupt the microprocessor when accessed by the VMEbus.
Interrupt Handler: The interrupt handler monitors, and can be
programmed to respond to any or all VMEbus IRQ* lines. All normal
process VMEbus-related interrupts can be mapped to PCI INTA# or
SERR# interrupts. These include:
Mailbox interrupts
VMEbus interrupts
VMEbus interrupter IACK cycle (acknowledgment of VMIVME-7807
VMEbus-issued interrupts)
All error processing VMEbus-related interrupts can be mapped to PCI
INTA# or SERR#. Note: PCI SERR# initiates an SBC NMI. These include:
ACFAIL* interrupt
BERR* interrupt
SYSFAIL* interrupt
The interrupt handler has a corresponding STATUS/ID register for each
IRQ* interrupt. Once the handler receives an IRQ*, it requests the
VMEbus and, once granted, it performs an IACK cycle for that level.
Once the IACK cycle is complete and the STATUS/ID is stored in the
corresponding ID register, an appropriate interrupt status bit is set in an
internal status register and a PCI interrupt is generated. The PCI
interrupt can be mapped to PCI INTA# or SERR#.

Interrupter: Interrupts can be issued under software control on any or
all of the seven VMEbus interrupt lines (IRQ7* to IRQ1*). A common ID
register is associated with all interrupt lines. During the interrupt
acknowledge cycle, the interrupter issues the ID to the interrupt
handler.
The interrupter can be programmed to generate a PCI INTA# or SERR#
interrupt when a VMEbus interrupt handler acknowledges a softwaregenerated VMEbus interrupt.
Byte Swapping: The Intel 80×86 family of processors uses little-endian
format. To accommodate other VMEbus modules that transfer data in
big-endian format (such as the 680×0 processor family), the
VMIVME-7807 incorporates byte-swapping hardware. This provides
independent byte swapping for both the master and slave interfaces.
Both master and slave interface byte swapping are under software
control.
The VMIVME-7807 supports high throughput DMA transfers of bytes,
words and longwords in both master and slave configurations.
If endian conversion is not needed, we offer a special “bypass” mode
that can be used to further enhance throughput. (Not available for byte
transfers.)

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