IS200VAICH1B GE Embedded Ethernet interface

In an SNTP system, a computer on the network (called an SNTP server) sends out a periodic timing
message to all SNTP-capable Ethernet Interfaces on the network, which synchronize their internal
clocks with this SNTP timing message. If SNTP is used to perform network time synchronization, the
time-stamp information typically has ±10ms accuracy between controllers on the same network.
Synchronizing the CPU TOD clock to an SNTP server allows you to set a consistent time across multiple
systems. Once the CPU TOD clock has been synchronized with the SNTP time, all produced EGD
exchanges will use the CPU TOD current value for the time-stamp.
The CPU TOD clock is set with accuracy within ±2ms of the SNTP time-stamp.
TOD clock synchronization is enabled on an Ethernet module by the advanced user parameter (AUP),
ncpu_sync. The CPU must also use a COMMREQ in user logic to select an Ethernet module as the time
master. For additional information, refer to Time-stamping of Ethernet Global Data Exchanges in
PACSystems RX7i, RX3i and RSTi-EP TCP/IP Ethernet Communications User Manual, GFK-2224 Chapter 4.
A software watchdog timer in the CPU is designed to detect failure to complete sweep conditions. The
timer value for the software watchdog timer is set by using the programming software. The allowable
range for this timer is 10 ms to 2550 ms; the default value is 200 ms. The software watchdog timer
always starts from zero at the beginning of each sweep.

The software watchdog timer is useful in detecting abnormal operation of the application program
that prevents the CPU sweep from completing within the user-specified time. Examples of such
abnormal application program conditions are as follows:
▪ Excessive recursive calling of a block
▪ Excessive looping (large loop count or large amounts of execution time for each iteration)
▪ Infinite execution loop
When selecting a software watchdog value, always set the value higher than the longest expected
sweep time to prevent accidental expiration. For Constant Sweep mode, allowance for over sweep
conditions should be considered when selecting the software watchdog timer value.
Refer to the Appendix A-3.6 for EGD Sweep impact and EGD processor utilization for EGD exchanges
configured on Embedded Ethernet interface of the RX3i CPE305/310 and RSTi-EP CPE100.
The watchdog timer continues during interrupt execution. Queuing of interrupts within a single sweep
may cause watchdog timer expiration.
If the software watchdog timeout value is exceeded, the OK LED blinks, and the CPU goes to STOP-Halt
mode69. Certain functions, however, are still possible. A fault is placed in the CPU fault table, and
outputs go to their default state. The CPU will only communicate with the programmer; no other
communications or operations are possible. To recover, power must be cycled on the rack or
backplane containing the CPU.

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